Kioxia’s booth at FMS 2024 attracted significant attention with multiple technology demonstrations engaging visitors. The first notable feature was a walk-through of the BiCS 8 manufacturing process. Kioxia and Western Digital announced the sampling of BiCS 8 in March 2023. We had previously touched upon its CMOS Bonded Array (CBA) scheme in our discussions of Kioxia’s 2Tb QLC NAND device and Western Digital’s 128 TB QLC enterprise SSD proof-of-concept demonstration. At Kioxia’s booth, we gained more insights.
Traditionally, flash chip fabrication involved the placement of associated logic circuitry (CMOS process) around the flash array’s periphery. The process evolved to placing the CMOS under the cell array, with the development process being serialized—fabricating the CMOS logic first and then the cell array on top. This presented challenges because the cell array requires high-temperature processing to ensure higher reliability, which can be detrimental to the CMOS logic’s health. Thanks to advancements in wafer bonding techniques, the new CBA process allows the CMOS wafer and cell array wafer to be processed independently in parallel and then combined, as shown in the models above.
The BiCS 8 3D NAND incorporates 218 layers, compared to 112 layers in BiCS 5 and 162 layers in BiCS 6. The company opted to skip BiCS 7 (likely a short-lived generation meant as an internal test vehicle). This generation retains the four-plane charge trap structure of BiCS 6. In its TLC variant, it is available as a 1 Tbit device. The QLC version comes in two capacities—1 Tbit and 2 Tbit.
Kioxia also noted that while the 218 layers might not match the latest layer counts from competitors, its lateral scaling/cell shrinkage allows it to remain competitive in terms of bit density and operating speeds (3200 MT/s). For reference, Micron’s latest shipping NAND—the G9—has 276 layers with a bit density in TLC mode of 21 Gbit/mm2 and operates at up to 3600 MT/s. However, its 232L NAND operates only up to 2400 MT/s and has a bit density of 14.6 Gbit/mm2.
It is worth noting that the CBA hybrid bonding process offers advantages over current processes used by other vendors, such as Micron’s CMOS under array (CuA) and SK hynix’s 4D PUC (periphery-under-chip), developed in the late 2010s. It is expected that other NAND vendors will eventually adopt some variant of the hybrid bonding scheme used by Kioxia.
