TSMC recently shared its plans to initiate high-volume manufacturing with its N3P fabrication process later this year, marking a significant milestone as its most sophisticated node to date. In 2025, TSMC aims to further push the envelope with two new process technologies poised for high-volume manufacturing (HVM) in the latter half of the year, potentially setting the stage for internal competition.
| Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases |
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| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
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| Power | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Performance | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | Q4 2022 |
Q4 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density published by TSMC reflects a ‘mixed’ chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same area.
***At the same speed.
The production nodes N3X (3nm-class, focused on extreme performance) and N2 (2nm-class) represent significant advancements in TSMC’s technology. The N3X node offers several key enhancements over N3P, such as the ability to reduce power consumption by 7% at the same frequency by lowering Vdd from 1.0V to 0.9V, improve performance by 5% at the same area, or increase transistor density by approximately 10% at the same frequency. Furthermore, N3X’s maximum voltage of 1.2V is crucial for ultra-high-performance applications like desktop or datacenter GPUs.
N2, TSMC’s first production node to leverage gate-all-around (GAA) nanosheet transistors, will greatly improve its power, performance, and area (PPA) characteristics. In comparison with N3E, N2 can reduce power consumption by 25% – 30%, enhance performance by 10% – 15%, and boost transistor density by 15%, all at the same transistor count and frequency.
While N2 is set to lead in power consumption and transistor density, N3X could challenge it in terms of performance, particularly at higher voltages. The use of proven FinFET transistors with N3X also provides an advantage for many customers over the newer N2 node in the second half of 2025.
2026: Targeting Smartphones and High-Performance Computing
Looking ahead to 2026, TSMC plans to introduce two nodes aimed at smartphones and high-performance computing: N2P (a performance-enhanced 2nm-class) and A16 (1.6nm-class with backside power delivery).
N2P is expected to offer 5% – 10% lower power consumption or 5% – 10% improved performance in comparison to the original N2 node, based on the same speed and transistor count. The A16 node aims to reduce power usage by up to 20% or boost performance up to 10% while also providing up to 10% higher transistor density compared to N2P.
A16’s notable feature includes an enhanced backside power delivery network, positioning it as the preferred choice for performance-oriented chip design, albeit at a higher cost due to the additional processing steps required for backside power delivery.
